Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation
Journal article
Zhai, Xiaojun, Ramalingam, Soodamani and Bensaali, Faycal 2013. Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation. IET Circuits, Devices & Systems. https://doi.org/10.1049/iet-cds.2012.0064
| Authors | Zhai, Xiaojun, Ramalingam, Soodamani and Bensaali, Faycal |
|---|---|
| Abstract | Number plate localisation is a very important stage in an automatic number plate recognition (ANPR) system and is computationally intensive. This study presents a low complexity with high-detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplier-less architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (field programmable gate arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images, respectively, both with a resolution of 640 x 480, have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms, while achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA. |
| Keywords | Image processing; FPGA; Recognition |
| Year | 2013 |
| Journal | IET Circuits, Devices & Systems |
| Publisher | The Institution of Engineering and Technology |
| ISSN | 1751-858X |
| 1751-8598 | |
| Digital Object Identifier (DOI) | https://doi.org/10.1049/iet-cds.2012.0064 |
| Web address (URL) | http://hdl.handle.net/10545/583879 |
| hdl:10545/583879 | |
| Publication dates | 01 Mar 2013 |
| Publication process dates | |
| Deposited | 14 Dec 2015, 10:53 |
| Series | Vol. 7 |
| Issue 2 | |
| Rights | Archived with thanks to IET Circuits, Devices & Systems |
| Contributors | University of Hertfordshire |
| File | File Access Level Open |
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