Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation

Thesis


Rathnala, Prasanthi 2017. Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation. Thesis
AuthorsRathnala, Prasanthi
Abstract

Growing usage of smart and portable electronic devices demands embedded system designers to provide solutions with better performance and reduced power consumption. Due to the new development of IoT and embedded systems usage, not only power and performance of these devices but also security of them is becoming an important design constraint. In this work, a novel aggressive scaling based on timing speculation is proposed to overcome the drawbacks of traditional DVFS and provide security from power analysis attacks at the same time. Dynamic voltage and frequency scaling (DVFS) is proven to be the most suitable technique for power efficiency in processor designs. Due to its promising benefits, the technique is still getting researchers attention to trade off power and performance of modern processor designs. The issues of traditional DVFS are: 1) Due to its pre-calculated operating points, the system is not able to suit to modern process variations. 2) Since Process Voltage and Temperature (PVT) variations are not considered, large timing margins are added to guarantee a safe operation in the presence of variations. The research work presented here addresses these issues by employing aggressive scaling mechanisms to achieve more power savings with increased performance. This approach uses in-situ timing error monitoring and recovering mechanisms to reduce extra timing margins and to account for process variations. A novel timing error detection and correction mechanism, to achieve more power savings or high performance, is presented. This novel technique has also been shown to improve security of processors against differential power analysis attacks technique. Differential power analysis attacks can extract secret information from embedded systems without knowing much details about the internal architecture of the device. Simulated and experimental data show that the novel technique can provide a performance improvement of 24% or power savings of 44% while occupying less area and power overhead. Overall, the proposed aggressive scaling technique provides an improvement in power consumption and performance while increasing the security of processors from power analysis attacks.

Growing usage of smart and portable electronic devices demands embedded system designers to provide solutions with better performance and reduced power consumption. Due to the new development of IoT and embedded systems usage, not only power and performance of these devices but also security of them is becoming an important design constraint. In this work, a novel aggressive scaling based on timing speculation is proposed to overcome the drawbacks of traditional DVFS and provide security from power analysis attacks at the same time.
Dynamic voltage and frequency scaling (DVFS) is proven to be the most suitable technique for power efficiency in processor designs. Due to its promising benefits, the technique is still getting researchers attention to trade off power and performance of modern processor designs. The issues of traditional DVFS are: 1) Due to its pre-calculated operating points, the system is not able to suit to modern process variations. 2) Since Process Voltage and Temperature (PVT) variations are not considered, large timing margins are added to guarantee a safe operation in the presence of variations.
The research work presented here addresses these issues by employing aggressive scaling mechanisms to achieve more power savings with increased performance. This approach uses in-situ timing error monitoring and recovering mechanisms to reduce extra timing margins and to account for process variations. A novel timing error detection and correction mechanism, to achieve more power savings or high performance, is presented. This novel technique has also been shown to improve security of processors against differential power analysis attacks technique. Differential power analysis attacks can extract secret information from embedded systems without knowing much details about the internal architecture of the device. Simulated and experimental data show that the novel technique can provide a performance improvement of 24% or power savings of 44% while occupying less area and power overhead. Overall, the proposed aggressive scaling technique provides an improvement in power consumption and performance while increasing the security of processors from power analysis attacks.

KeywordsDifferential power analysis; Dynamic voltage and frequency scaling; Internet of things; S-Box; Low power performance improvement; Time-Borrowing; Timing Error; Aggressive Scaling; Process voltage and temperature
Year2017
Web address (URL)http://hdl.handle.net/10545/621716
http://creativecommons.org/licenses/by/4.0/
hdl:10545/621716
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Publication process dates
Deposited30 Jun 2017, 09:04
Publication datesMay 2017
ContributorsUniversity of Derby
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https://repository.derby.ac.uk/item/94q6q/power-efficient-and-power-attacks-resistant-system-design-and-analysis-using-aggressive-scaling-with-timing-speculation

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Related outputs

Timing error detection and correction for power efficiency: an aggressive scaling approach
Rathnala, Prasanthi, Wilmshurst, Tim and Kharaz, Ahmad H. 2018. Timing error detection and correction for power efficiency: an aggressive scaling approach. IET Circuits, Devices & Systems. https://doi.org/10.1049/iet-cds.2018.5143